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d a t a sh eet product speci?cation supersedes data of november 1994 file under integrated circuits, ic03 1995 jun 27 integrated circuits UMA1018M low-voltage dual frequency synthesizer for radio telephones
1995 jun 27 2 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M features low current from 3 v supply fully programmable rf divider 3-line serial interface bus second synthesizer to control first if or offset loop frequency independent fully programmable reference dividers for each loop, driven from external crystal oscillator dual phase detector outputs to allow fast frequency switching integrated digital-to-analog converter dual power-down modes. applications 900 mhz mobile telephones portable battery-powered radio equipment. general description the UMA1018M bicmos device integrates prescalers, programmable dividers, and phase comparators to implement two phase-locked loops. the device is designed to operate from 3 nicd cells, in pocket phones, with low current and nominal 5 v supplies. the principal synthesizer operates at rf input frequencies up to1.25 ghz the auxiliary synthesizer operates at 300 mhz. the auxiliary loop is intended for the first if or to transmit offset loop-frequency settings. each synthesizer has a fully programmable reference divider. all divider ratios are supplied via a 3-wire serial programming bus. separate power and ground pins are provided to the analog and digital circuits. the ground leads should be externally short-circuited to prevent large currents flowing across the die and thus causing damage. digital supplies v dd1 and v dd2 must also be at the same potential. v cc must be equal to or greater than v dd (i.e. v dd = 3 v and v cc = 5 v for wider tuning range). the principal synthesizer phase detector uses two charge pumps, one provides normal loop feedback, while the other is only active during fast mode to speed-up switching. the auxiliary loop has a separate phase detector. all charge pump currents (gain) are fixed by an external resistance at pin i set (pin 14). only passive loop filters are used; the charge-pumps function within a wide voltage compliance range to improve the overall system performance. an on-chip 7-bit dac enables adjustment of an external function, such as the temperature compensation of a crystal oscillator in global system for mobile communications (gsm). quick reference data symbol parameter conditions min. typ. max. unit v cc , v dd supply voltage v cc 3 v dd 2.7 - 5.5 v i cc +i dd principal synthesizer supply current auxiliary synthesizer in power-down mode - 7.7 - ma principal and auxiliary synthesizer supply current principal and auxiliary synthesizers on - 10 - ma i ccpd , i ddpd current in power-down mode per supply - 12 -m a f vco principal input frequency 50 - 1250 mhz f ai auxiliary input frequency 20 - 300 mhz f xtal crystal reference input frequency 3 - 40 mhz f ppc principal phase comparator frequency - 200 - khz f apc auxiliary phase comparator frequency - 200 - khz t amb operating ambient temperature - 30 - +85 c
1995 jun 27 3 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M ordering information block diagram type number package name description version UMA1018M ssop20 plastic shrink small outline package; 20 leads; body width 4.4 mm sot266-1 fig.1 block diagram.
1995 jun 27 4 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M pinning symbol pin description fast 1 control input to speed-up main synthesizer cppf 2 principal synthesizer speed-up charge-pump output cpp 3 principal synthesizer normal charge-pump output v dd1 4 digital power supply 1 v dd2 5 digital power supply 2 pri 6 1 ghz principal synthesizer frequency input dgnd 7 digital ground f xtal 8 common crystal frequency input from tcxo pon 9 principal synthesizer power-on input dout 10 7-bit digital-to-analog output clk 11 programming bus clock input data 12 programming bus data input e 13 programming bus enable input (active low) i set 14 regulator pin to set the charge-pump currents aux 15 auxiliary synthesizer frequency input agnd 16 analog ground cpa 17 auxiliary synthesizer charge-pump output v cc 18 supply for charge-pump and dac circuits aon 19 auxiliary synthesizer power-on input lock 20 in-lock detect output (main pll); test mode output fig.2 pin configuration. functional description principal synthesizer programmable reference and main dividers drive the principal pll phase detector. two charge pumps produce phase error current pulses for integration in an external loop filter. a hardwired power-down input pon (pin 9) ensures that the dividers and phase comparator circuits can be disabled. the pri input (pin 6) drives a pre-amplifier to provide the clock to the first divider stage. the pre-amplifier has a high input impedance, dominated by pin and pad capacitance. the circuit operates with signal levels from 50 mv up to 225 mv (rms), and at frequencies as high as 1.25 ghz. the high frequency divider circuits use bipolar transistors, slower bits are cmos. divider ratios (512 to 131 071) allow a 1 mhz phase comparison with a 500 mhz rf input, and a 10 khz phase comparison with a 1.25 ghz rf input. the reference and main divider outputs are connected to a phase/frequency detector that controls two charge pumps. the two pumps have a common bias-setting current that is set by an external resistance. the ratio between currents in fast and normal operating modes can be programmed via the 3-wire serial bus. the low current pump remains active except in power-down.
1995 jun 27 5 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M the high current pump is enabled via the control input fast (pin 1). by appropriate connection to the loop filter, dual bandwidth loops are provided: short time constant during frequency switching (fast mode) to speed-up channel changes and low bandwidth in the settled state (on-frequency) to reduce noise and breakthrough levels. the principal synthesizer speed-up charge pump (cppf) is controlled by the fast input in synchronization with phase detector operation in such a way that potential disturbances are minimized. the dead zone (caused by finite time taken to switch the current sources on or off) is cancelled by feedback from the normal pump output to the phase detector thereby improving linearity. an open drain transistor drives the output pin lock (pin 20). it is recommended that the pull-up resistor from this pin to v dd is chosen such that the value is high enough to keep the sink current in the low state below 400 m a. the circuit can be programmed to output either the phase error in the principal or auxiliary phase detectors or the combination from both detectors (or function). the resultant output will be a current pulse with the duration of the selected phase error. by appropriate external filtering and threshold comparison an out-of-lock or an in-lock flag is generated. auxiliary synthesizer the auxiliary synthesizer has a 14-bit main divider and an 11-bit reference divider. a separate power-down input aon (pin 19), disables currents in the auxiliary dividers, phase detector, and charge pump. the auxiliary input signal is amplified and fed to the main divider. the input buffer presents a high impedance, dominated by pin and pad capacitance. first divider stages use bipolar technology operating at input frequencies up to 300 mhz; the slower bits are cmos. the auxiliary loop phase detector and charge pump use similar circuits to the main loop low-current phase comparator, including dead-zone compensation feedback. the auxiliary reference divider is clocked on the opposite edge of the principal reference divider to ensure that active edges arrive at the auxiliary and principal phase detectors at different times. this minimizes the potential for interference between the charge pumps of each loop. serial programming bus a simple 3-line unidirectional serial bus is used to program the circuit. the 3 lines are data, clk and e (enable). the data sent to the device is loaded in bursts framed by e. programming clock edges and their appropriate data bits are ignored until e goes active low. the programmed information is loaded into the addressed latch when e returns inactive high. only the last 21 bits serially clocked into the device are retained within the programming register. additional leading bits are ignored, and no check is made on the number of clock pulses. the fully static cmos design uses virtually no current when the bus is inactive. it can always capture new programmed data even during power-down of main and auxiliary loops. however, when either principal synthesizer or auxiliary synthesizer or both are powered-on, the presence of a tcxo signal is required at pin 8 (f xtal ) for correct programming. data format data is entered with the most significant bit first. the leading bits make up the data field, while the trailing four bits are an address field. the UMA1018M uses 6 of the 16 available addresses. these are chosen to allow direct compatibility with the uaa2072m integrated front-end. the data format is shown in table 1. the first entered bit is p1, the last bit is p21. the trailing address bits are decoded on the inactive edge of e. this produces an internal load pulse to store the data in one of the addressed latches. to ensure that the data is correctly loaded on first power-up, e should be held low and only taken high after having programmed an appropriate register. to avoid erroneous divider ratios, the pulse is not allowed during data reads by the frequency dividers. this condition is guaranteed by respecting a minimum e pulse width after data transfer. the corresponding relationship between data fields and addresses is given in table 2.
1995 jun 27 6 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M table 1 format of programmed data table 2 bit allocation (note 1) notes 1. ft = first; lt = last; spon = software power-up for principal synthesizer (1 = on); saon = software power-up for auxiliary synthesizer (1 = on). 2. the test register should not be programmed with any other value except all zeros for normal operation. table 3 out-of-lock select last in programming register bit usage first in p21 p20 p19 p18 p17 p16 ../.. p2 p1 add0 add1 add2 add3 data0 data1 ../.. data15 data16 latch address lsb data coefficient msb ft register bit allocation lt p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 dt16 dt15 dt14 dt13 dt12 data field dt4 dt3 dt2 dt1 dt0 address test bits (2) 0000 x x x x olp ola cr1 cr0 x x spon saon x x x x x 0001 pm16 principal main divider coefficient pm0 0100 x x x x x x pr10 principal reference divider coefficient pr0 0101 x x x am13 auxiliary main divider coefficient am0 0110 x x x x x x ar10 auxiliary reference divider coefficient ar0 0111 x x x x x x x x x 0 da6 7-bit dac da0 1000 olp ola out-of-lock on pin 20 0 0 output disabled 0 1 auxiliary phase error 1 0 principal phase error 1 1 both auxiliary and principal
1995 jun 27 7 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M table 4 fast and normal charge pumps current ratio (note 1) note 1. ; common bias current for charge pumps and dac. table 5 power-down modes cr1 cr0 i cpa i cpp i cppf i cppf :i cpp 00 4 i set 4 i set 16 i set 4:1 01 4 i set 4 i set 32 i set 8:1 10 4 i set 2 i set 24 i set 12:1 11 4 i set 2 i set 32 i set 16:1 aon pon fast principal dividers auxiliary dividers pump cpa pump cpp pump cppf dac and bias 0 0 x off off off off off off 0 1 0 on off off on off on 0 1 1 on off off on on on 1 0 x off on on off off on 1 1 0 on on on on off on 111 on on ononon on i set v 14 r ext ---------- - = digital-to-analog converter the 7-bits loaded via the bus into the appropriate latch drive a digital-to-analog converter. the internal current is scaled by the external resistance (r ext ) at pin i set , similar to the charge pumps. the nominal full-scale current is 2 i set . the output current is mirrored to produce a full-scale voltage into a user-defined ground referenced resistance, thereby allowing optimum swing from power supply rails within the 2.7 to 5.5 v limits. the band gap reference voltage at pin i set is temperature and supply independent. the dac signal is monotonic across the full range of digital input codes to enable fine adjustment of other system blocks. the typical settling time for full-scale switching is 400 ns into a 12 k w // 20 pf load. dac functionality is neither tested nor guaranteed on UMA1018M versions with the /s1 suffix. power-down modes the action of the control inputs on the state of internal blocks is defined by table 5. it should be noted that in table 5, pon and aon can be either the software or hardware power-down signals. the dividers are on when both hardware and software power-down signals are at logic 1. when either synthesizer is reactivated after power-down the main and reference dividers of that synthesizer are synchronized to avoid the possibility of random phase errors on power-up.
1995 jun 27 8 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M limiting values in accordance with the absolute maximum rating system (iec 134). handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. thermal characteristics symbol parameter min. max. unit v dd digital supply voltage - 0.3 +5.5 v v cc analog supply voltage - 0.3 +5.5 v d v cc - dd difference in voltage between v cc and v dd - 0.3 +5.5 v v n voltage at pins 1, 6, 8 to 15, 19 and 20 - 0.3 v dd + 0.3 v v 2, 3, 17 voltage at pins 2, 3 and 17 - 0.3 v cc + 0.3 v d v gnd difference in voltage between agnd and dgnd (these pins should be connected together) - 0.3 +0.3 v p tot total power dissipation - 150 mw t stg storage temperature - 55 +125 c t amb operating ambient temperature - 30 +85 c t j maximum junction temperature - 95 c symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 120 k/w
1995 jun 27 9 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M characteristics v dd1 =v dd2 = 2.7 to 5.5 v; v cc = 2.7 to 5.5 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply; pins 4, 5 and 18 v dd digital supply voltage v dd1 =v dd2 2.7 - 5.5 v v cc analog supply voltage v cc 3 v dd 2.7 - 5.5 v i dd principal synthesizer digital supply current v dd = 5.5 v - 6.5 8.5 ma auxiliary synthesizer digital supply current v dd = 5.5 v - 2.7 4.0 ma i cc charge pumps and analog supply current v cc = 5.5 v; r ext =12k w - 1.2 2.0 ma i ccpd , i ddpd current in power-down mode per supply logic levels 0 v or v dd - 12 50 m a rf principal main divider input; pin 6 f vco rf input frequency 2. 7v 1995 jun 27 10 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M auxiliary main divider input; pin 15 f ai input frequency 20 - 300 mhz v 15(rms) ac-coupled input signal level (rms value) r s =50 w ; 2.7v 1995 jun 27 11 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M note 1. d i is the change in dac output current when making the code transitions: 3fh/40h or 1fh/20h. serial bus timing characteristics v dd =v cc =3v; t amb =25 c unless otherwise speci?ed. note 1. the minimum pulse width (t w ) can be smaller than 4 m s provided all the following conditions are satisfied: a) principal main divider input frequency b) auxiliary main divider input frequency c) reference divider input frequency dac output signal levels; pin 10; r ext =12to24k w i dac dac full scale output current 1.5 i set 2 i set 2.5 i set ma v 10 output voltage compliance all codes 0 - v dd - 0.4 v i 10min minimum dac current 00 code - 25 m a i monot worst case monotonicity test: note 1 0.1 - 1.9 lock detect output signal; pin 20; open-drain output v ol low level output voltage i sink = 0.4 ma -- 0.4 v symbol parameter min. typ. max. unit serial programming clock; clk t r input rise time - 10 40 ns t f input fall time - 10 40 ns t cy clock period 100 -- ns enable programming; e t start delay to rising clock edge 40 -- ns t end delay from last falling clock edge - 20 -- ns t w minimum inactive pulse width 4000 (1) -- ns t su; e enable set-up time to next clock edge 20 -- ns register serial input data; data t su;dat input data to clock set-up time 20 -- ns t hd;dat input data to clock hold time 20 -- ns symbol parameter conditions min. typ. max. unit d i 128 2i set -------------------- f vco 256 t w --------- - > f ai 32 t w ------ > f xtal 3 t w ----- - >
1995 jun 27 12 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M fig.3 serial bus timing diagram.
1995 jun 27 13 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M application information fig.4 typical application block diagram.
1995 jun 27 14 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M fig.5 typical test and application diagram. bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbbb bbbbbbbbbbb b bbbbbbbbb b b bbbbbbbbb b b bbbbbbbbb b b bbbbbbbbb b b bbbbbbbbb b b bbbbbbbbb b b bbbbbbbbb b b bbbbbbbbb b bbbbbbbbbbb bbbbbbbbbbb bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbb b bbbbbbbbbbb
1995 jun 27 15 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0 1.4 1.2 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 1.0 0.2 6.6 6.2 0.65 0.45 0.48 0.18 10 0 o o 0.13 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 0.75 0.45 sot266-1 90-04-05 95-02-25 w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a x (a ) 3 a y 0.25 110 20 11 pin 1 index 0 2.5 5 mm scale ssop20: plastic shrink small outline package; 20 leads; body width 4.4 mm sot266-1 a max. 1.5
1995 jun 27 16 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M soldering so or ssop introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these cases reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all so and ssop packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering so wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. ssop wave soldering is not recommended for ssop packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. even with these conditions, only consider wave soldering ssop packages that have a body width of 4.4 mm, that is ssop16 (sot369-1) or ssop20 (sot266-1) . m ethod (so or ssop) during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds at 270 to 320 c.
1995 jun 27 17 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1995 jun 27 18 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M notes
1995 jun 27 19 philips semiconductors product speci?cation low-voltage dual frequency synthesizer for radio telephones UMA1018M notes
philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40 783 749, fax. (31)40 788 399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil. p.o. box 7383 (01064-970), tel. (011)821-2333, fax. (011)829-1849 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. (571)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032)88 2636, fax. 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(0039)2 6752 2557 japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5130, fax. (03)3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)709-1412, fax. (02)709-1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb tel. (040)783749, fax. (040)788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546 philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366 singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430, johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494. spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (02)388 7666, fax. (02)382 4382 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (662)398-0141, fax. (662)398-3319 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 27 70, fax. (0212)282 67 07 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181)730-5000, fax. (0181)754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd40 ? philips electronics n.v. 1995 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 413061/1500/04/pp20 date of release: 1995 jun 27 document order number: 9397 750 00182

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